Memory register having an integrated delay-locked loop

ABSTRACT

A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

TECHNICAL FIELD

The present invention is related to memory applications and, inparticular, to a register for a memory device, the register having anintegrated delay-locked loop.

DISCUSSION OF RELATED ART

Dual In-Line Memory Modules (DIMMs) have become the industry standardfor supplying random access memory (RAM) for computer applications. EachDIMM is typically a printed circuit board that includes a number ofindividual RAM chips. The RAM chips can be any memory chips, for exampledynamic RAM (DRAM) chips or synchronous RAM (SRAM) chips. In some cases,the DIMM functions as a double data rate DIMM (DDR DIMM) where data isreceived both on the rising edge of the clock signal and on the fallingedge of the clock signal.

As the demand for memory density increases, DIIM packages that contain ahigher density of RAM chips become important. One such DIMM package is aregistered DIMM package (RDIMM). An RDIMM package includes one or moreregisters. The registers typically receive a clock signal and use thisto determine a point in time at which to store the input signal level,the input signal including, for example, address bits, which may then beused to drive the output to this level. For example, in an RDIMM,address bits received on the address lines are registered in one or moreregisters integrated onto the DIMM package before being presented to theRAM chips. The register acts as an electrical buffer, distributing thereceived memory address bits to each of the RDIMM RAM chips.

However, adding a register to a DIMM package often adds a delay betweenthe clock edge and the output swing, introducing delays and errors intothe signals being transmitted to the memory chips. For example, adding aregister to a DIMM package may introduce dynamic phase offset andjitter, both of which affect the timing margins of the DIMM, and thusadversely affect performance. To address these errors and delays, aphase-locked loop (PLL) may be used by the register to eliminate theerrors and delay. A PLL typically includes a phase comparator, a voltagecontrolled oscillator, and a feedback path. In operation, a PLL willtypically generate a signal that has a fixed relation to the phase of areference signal by automatically raising or lowering the frequency ofthe voltage controlled oscillator until it matches the frequency andphase of the reference signal. The PLL will compare the phase of thevoltage controlled oscillator with the reference signal to generate anerror signal, which is then twice integrated to generate a controlsignal that is fed back into the voltage controlled oscillator.

Although the PLL is able to eliminate the errors, it also introducesadditional delays into the signals, which also affect the performance ofthe DIMM. The PLL also does not allow for tuning the register to varythe skew of the output signals. Moreover, the voltage-controlledoscillator of the PLL increases power requirements for the DIMM, andintroduces additional dynamic phase offset and jitter into the signal.

There is therefore a need to account for the errors introduced by aregister in a registered DIMM while still increasing the performance ofthe DIMM.

SUMMARY

In accordance with aspects of the present invention, there is provided amemory device, comprising a plurality of memory chips coupled in series;and a register serially coupled to the memory chips, wherein theregister includes an integrated delay-locked loop.

In accordance with aspects of the present invention, there is alsoprovided a processing system, comprising a processor; and a randomaccess memory device coupled to the processor through a bus, the randomaccess memory device comprising at least one register; and adelay-locked loop integrated in the register.

In accordance with aspects of the present invention, there is furtherprovided a method for improving timing budgets in a registered dualin-line memory module (RDIMM) having a register which receives an inputclock signal, the method comprising: providing a delay-locked loop inthe register; receiving the input clock signal in the delay-locked loop;outputting an output clock signal from the delay-locked loop; comparinga phase of the output clock signal to a phase of the input clock signal;generating an error signal based on the comparison; integrating theerror signal to generate a delay control signal; and delaying the outputclock signal by a predetermined amount based on the control signal.

These and other embodiments will be described in further detail belowwith respect to the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an RDIMM package, consistent with the presentinvention.

FIG. 2 illustrates register incorporating a delay-locked loop (DLL),consistent with the present invention.

FIG. 3 is a flowchart illustrating a method for delaying a clock signalusing a DLL, consistent with the present invention.

In the drawings, elements having the same designation have the same orsimilar functions.

DETAILED DESCRIPTION

In the following description specific details are set forth describingcertain embodiments of the invention. It will be apparent, however, toone skilled in the art that the present invention may be practicedwithout some or all of these specific details. The specific embodimentspresented are meant to be illustrative of the present invention, but notlimiting. One skilled in the art may realize other material that,although not specifically described herein, is within the scope andspirit of this disclosure.

FIG. 1 illustrates a memory device 100 consistent with the presentinvention. In accordance with aspects of the present invention, memorydevice 100 may be a registered dual in-line memory module (RDIMM)package 100. Consistent with the present invention, RDIMM 100 may be arandom access memory device in a processing system including aprocessor, such as, for example, a computer system.

RDIMM package 100 includes individual memory chips 101-1 through 101-N,coupled in series. Consistent with the present invention, individualmemory chips may be random access memory (RAM) chips or dynamic randomaccess memory (DRAM) chips.

As shown in FIG. 1, RDIMM package includes a register 102, which isserially coupled to memory chip 101-1. Consistent with embodiments ofthe present invention, register 102 may be coupled to any of memorychips 101-1 through 101-N. Register 102 resides in RDIMM package 100,and may drive the inputs of more RAM chips than could otherwise besupported in RDIMM package 100. For example, as shown in FIG. 1,register 102 is coupled to address line 104, control line 106, and clockline 108 to receive an address signal, a control signal, and a clocksignal. Register 102 may then drive the address signal and the controlsignal through memory chips 101-1 through 101-N, and may buffer theclock signal before transmitting the clock signal through memory chips101-1 through 101-N.

Memory chips 101-1 through 101-N are all coupled to data lines 110 toreceive and transmit data, strobe lines 112 to receive and transmitstrobe (DSQ/DSQ#) signals, as well as address lines 104 to receive theaddress signal, and control lines 106 to receive control signals. Memorychips 101-1 through 101-N are also coupled to clock line 108 to receivethe clock signal. Consistent with embodiments of the present invention,at least one of memory chips 101-1 through 101-N may be coupled to aresistance, which may be a terminal resistance. In one specificembodiment, a first memory chip 101-1 is coupled to a first terminalresistance (not shown), and a last memory chip 101-N is coupled to asecond terminal resistance (not shown).

FIG. 2 illustrates register 102 incorporating a delay-locked loop (DLL)200, consistent with the present invention. As shown in FIG. 2, addresslines 104 and control lines 106 are coupled to a buffer 202 whichtemporarily stores the address and control signals, and then drives theaddress and control signals through memory chips 101-1 through 101-N.DLL 200 is coupled to clock line 108 and receives and buffers the clocksignal by delaying the clock signal by a predetermined amount. DLL 200includes a phase detector 204 and a plurality of variable delay gates206-1 through 206-N. As shown in FIG. 2, delay gates 206-1 through 206-Nare coupled in series, and phase detector 204 is coupled in parallelwith each delay gate 206-1 through 206-N.

The operation of DLL 200 will be explained with reference to FIG. 3.FIG. 3 is a flowchart illustrating a method for delaying a clock signalusing a DLL, consistent with the present invention. A clock signalcarried on clock line 108 is input into DLL 200, and into delay gates206-1 through 206-N (step 302). The clock signal is then transmittedthrough variable delay gates 206-1 through 206-N which delays the clocksignal by a predetermined amount. The output clock signal is then outputfrom DLL 200 into buffer 202 and into memory chips 101-1 through 101-N(step 304). Phase detector 204 samples the input clock signal and theoutput clock signal, and compares the phase of the output clock signalwith the input clock signal (step 306). Based on the comparison, phasedetector 204 generates an error signal (step 308) which is thenintegrated in the phase detector to generate a delay control signal(step 310). The delay control signal is input into each variable delaygate 206-1 through 206-N which delays the clock signal by apredetermined amount (step 312). The delayed clock signal is then outputfrom DLL 200 and input into memory chips 101-1 through 101-N (step 314).Consistent with the present invention, the integration forces the errorto go to zero, while maintaining a phase lock between the input andoutput clock signals. By avoiding the internal oscillator of thestandard PLL, DLL 200 is able to reduce the errors associated with, forexample, dynamic phase offset and jitter, and timings associated withtracking the jitter, while using less power than a PLL-based registerand improving timing budgets.

Embodiments consistent with the present invention may improve timingbudgets of RDIMM 100 by delaying the clock signal with DLL 200integrated in register 102 of RDIMM 100. In particular, using a DLL 200in register 102 of RDIMM 100 may reduce errors in a clock signal, whileusing less power than a standard PLL. Moreover, register 102 havingintegrated DLL 200 may be used in memory devices designed to meet theJEDEC DDR3 specification.

For illustrative purposes, embodiments of the invention have beenspecifically described above. This disclosure is not intended to belimiting. Therefore, the invention is limited only by the followingclaims.

1. A memory device, comprising: a plurality of memory chips coupled inseries; and a register serially coupled to the memory chips, wherein theregister includes an integrated delay-locked loop.
 2. The memory deviceof claim 1, wherein the register receives an address signal, a controlsignal and at least one clock signal.
 3. The memory device of claim 2,wherein the register drives the address signal and the control signalthrough the memory chips, and the register buffers the at least oneclock signal.
 4. The memory device of claim 2, wherein the delay-lockedloop receives the at least one clock signal and outputs a delayed clocksignal having a predetermined delay.
 5. The memory device of claim 2,wherein the delay-locked loop comprises: a plurality of variable delaygates coupled in series, at least one of the plurality of delay gatesreceiving the at least one clock signal and at least one of theplurality of delay gates outputting a delayed clock signal having apredetermined delay; and a phase detector coupled in parallel to theplurality of delay gates, wherein: the phase detector receives the atleast one clock signal; samples the delayed clock signal; compares theat least one clock signal to the delayed clock signal; generates a delaycontrol signal based on the comparison of the at least one clock signalto the delayed clock signal; and the predetermined delay is controlledby the delay control signal.
 6. The memory device of claim 5, whereinthe memory device has an associated dynamic phase offset and anassociated error, and the delay-locked loop reduces the timing of thedynamic phase offset and reduces the timing for tracking the associatederror.
 7. The memory device of claim 1, wherein the memory chipscomprise dynamic random access memory (DRAM) chips.
 8. The memory deviceof claim 1, wherein the memory device comprises a registered dualin-line memory module (RDIMM).
 9. A processing system, comprising: aprocessor; and a random access memory device coupled to the processorthrough a bus, the random access memory device comprising: at least oneregister; and a delay-locked loop integrated in the register.
 10. Theprocessing system of claim 9, wherein the random access memory devicefurther comprises: a plurality of memory chips coupled in series, theregister being coupled in series to at least one of the memory chips.11. The processing system of claim 9, wherein the at least one registerreceives an address signal, a control signal and at least one clocksignal.
 12. The processing system of claim 11, wherein the at least oneregister drives the address signal and the control signal through thememory chips, and the register buffers the at least one clock signal.13. The processing system of claim 11, wherein the delay-locked loopreceives the at least one clock signal and outputs a delayed clocksignal having a predetermined delay.
 14. The processing system of claim11, wherein the delay-locked loop comprises: a plurality of variabledelay gates coupled in series, at least one of the plurality of delaygates receiving the at least one clock signal and at least one of theplurality of delay gates outputs a delayed clock signal having apredetermined delay; and a phase detector coupled in parallel to theplurality of delay gates, wherein: the phase detector receives the atleast one clock signal; samples the delayed clock signal; compares theat least one clock signal to the delayed clock signal; generates a delaycontrol signal based on the comparison of the at least one clock signalto the delayed clock signal; and the predetermined delay is controlledby the delay control signal.
 15. The processing system of claim 14,wherein the random access memory device has an associated dynamic phaseoffset and an associated error, and the delay-locked loop reduces thetiming of the dynamic phase offset and reduces the timing for trackingthe associated error.
 16. The processing system of claim 9, wherein therandom access memory device comprises a registered dual in-line memorymodule (RDIMM).
 17. The processing system of claim 10, wherein thememory chips comprise dynamic random access memory (DRAM) chips.
 18. Amethod for improving timing budgets in a registered dual in-line memorymodule (RDIMM) having a register which receives an input clock signal,the method comprising: providing a delay-locked loop in the register;receiving the input clock signal in the delay-locked loop; outputting anoutput clock signal from the delay-locked loop; comparing a phase of theoutput clock signal to a phase of the input clock signal; generating anerror signal based on the comparison; integrating the error signal togenerate a delay control signal; and delaying the output clock signal bya predetermined amount based on the control signal.